Compact Matched Filter for Integrand Code Using a Real-Valued Shift-Orthogonal Finite-Length Sequence
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概要
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In this paper, we proposed the compact construction of a matched filter for integrand code, which do not require the high-rate clock pulse in two-valued PWM (pulse width modulation) code, using a real-valued shift-orthogonal finite-length sequence, which has a sharp aperiodic autocorrelation function with zero sidelobes except at left and right shift-ends. This matched filters are implemented on a field programmable gate array (FPGA) corresponding to 400, 000 logic gates. A proposed matched filter for the sequence of length 129 can be constructed by the circuit scale of about 47% compared with conventional filter.
- (社)電子情報通信学会の論文
- 2010-11-01
著者
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MATSUMOTO Takahiro
Graduate School of Biological Sciences, Nara Institute of Science and Technology
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Matsumoto Takahiro
Graduate School Of Science And Engineering Yamaguchi University
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Matsumoto Takahiro
Graduate School Of Biological Sciences Nara Institute Of Science And Technology
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