Fourier Domain Decoding Algorithm of Non-binary LDPC Codes for Parallel Implementation
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概要
- 論文の詳細を見る
For decoding non-binary low-density parity-check (LDPC) codes, logarithm-domain sum-product (Log-SP) algorithms were proposed for reducing quantization effects of SP algorithm in conjunction with FFT. Since FFT is not applicable in the logarithm domain, the computations required at check nodes in the Log-SP algorithms are computationally intensive. What is worth, check nodes usually have higher degree than variable nodes. As a result, most of the time for decoding is used for check node computations, which leads to a bottleneck effect. In this paper, we propose a Log-SP algorithm in the Fourier domain. With this algorithm, the role of variable nodes and check nodes are switched. The intensive computations are spread over lower-degree variable nodes, which can be efficiently calculated in parallel. Furthermore, we develop a fast calculation method for the estimated bits and syndromes in the Fourier domain.
- （社）電子情報通信学会の論文
- 2010-11-01
著者
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SAKANIWA Kohichi
Dept. of Communications & Integrated Systems, Tokyo Institute of Technology
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Sakaniwa Kohichi
Dept. Of Communications And Integrated Systems Tokyo Institute Of Technology
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KASAI Kenta
Dept. of Communications and Integrated Systems, Tokyo Institute of Technology
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Kasai Kenta
Dept. Of Communications And Integrated Systems Tokyo Institute Of Technology
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KASAI Kenta
Dept. of Communications and Computer Engineering, Tokyo Institute of Technology
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