Noise Analysis and Design of Low-Noise Bias-Offset MOS Transconductor

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概要

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• High integration and low power operation of integrated circuits make noise sensitivity high. Therefore, it is important to reduce noise of circuits. A bias-offset transconductor is known as a linear transconductor. It is expected that noise sensitivity of the transconductor becomes higher due to improvement of linearity and reduction of power dissipation. This paper proposes a design method to reduce noise considering high linearity, reduction of power dissipation and small circuit size.

• 2011-01-01

著者

• MATSUMOTO Fujihiko

  National Defense Academy

• NOGUCHI Yasuaki

  National Defense Academy

• Nakamura Shintaro

  National Defense Academy

• TONGPOON Pravit

  National Defense Academy

関連論文

• Low-Voltage Linear OTAs Employing Multi-TANH Doublet and Exponential-Law Circuits
• Noise Analysis and Design of Low-Noise Bias-Offset MOS Transconductor

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