System Verilog-Based Verification Environment Employing Multiple Inheritance of SystemC

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概要

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• In this paper, we describe a verification environment which is based on a constrained random layered testbench using SystemVerilog OOP. As SystemVerilog OOP technique does not allow multiple inheritance, we adopt SystemC to design components of a verification environment which employ multiple inheritance. Then SystemC design unit is linked to a SystemVerilog-based verification environment using SystemVerilog DPI and ModelSim macro. Employing multiple inheritance of SystemC makes the design phase of verification environment simple and easy through source code reusability without corruption due to multi-level single inheritance.

• 2010-05-01

著者

• Song Gi-yong

  College Of Electrical & Computer Engineering Chungbuk National University

• YOU Myoung-Keun

  College of Electrical & Computer Engineering, Chungbuk National University

• You Myoung-keun

  College Of Electrical & Computer Engineering Chungbuk National University

関連論文

• System Verilog-Based Verification Environment Employing Multiple Inheritance of SystemC

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