Full Chip Circuit/Substrate Macro Modeling Method Which Controls the Analysis Accuracy and CPU Time by Using Current Density
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概要
- 論文の詳細を見る
Substrate noise analysis has become increasingly important in recent LSI design. This is because substrate noise, which affects PLLs, causes jitter that results in timing error. Conventional analysis techniques of substrate noise are, however, impractical for large-scale designs that have hundreds of millions of transistors because the computational complexity is too huge. To solve this problem, we have developed a fast substrate noise analysis technique for large-scale designs, in which a chip is divided into multiple domains and the circuits of each domain are reduced into a macro model. Using this technique, we have designed a processor chip for use in the supercomputer (die size: 20mm × 21mm, frequency: 3.2GHz, transistor count: 350M). Computation time with this design is five times faster than that with a 1/3000 scale design using a conventional technique, while resulting discrepancy with measured period jitter is less than 15%.
- （社）電子情報通信学会の論文
- 2010-02-01
著者
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KAJITA Mikihiro
NEC Corporation
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Kajita Mikihiro
Nec Corp.
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TANAKA Mikiko
NEC Electronics Corp.
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NAKAYAMA Naoya
NEC Electronics Corp.
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NAKAMOTO Satoshi
NEC Electronics Corp.
関連論文
- A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests
- Full Chip Circuit/Substrate Macro Modeling Method Which Controls the Analysis Accuracy and CPU Time by Using Current Density
- A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests