Complexity-Reducing Algorithm for Serial Scheduled Min-Sum Decoding of LDPC Codes

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概要

• 論文の詳細を見る

• We propose a complexity-reducing algorithm for serial scheduled min-sum decoding that reduces the number of check nodes to process during an iteration. The check nodes to skip are chosen based on the reliability, a syndrome and a log-likelihood-ratio (LLR) value, of the incoming messages. The proposed algorithm is evaluated by computer simulations and shown to reduce the decoding complexity about 20% compared with a conventional serial scheduled min-sum decoding with small fractional decibel degradation in error correction performance.

• （社）電子情報通信学会の論文
• 2009-10-01

著者

• UCHIKAWA Hironori

  Corporate R&D Center, Toshiba Corp.

• HARADA Kohsuke

  Corporate R&D Center, Toshiba Corp.

• Harada Kohsuke

  Corporate R&d Center Toshiba Corp.

• Uchikawa Hironori

  Corporate R&d Center Toshiba Corp.

関連論文

• Complexity-Reducing Algorithm for Serial Scheduled Min-Sum Decoding of LDPC Codes
• Complexity-Reducing Algorithm for Serial Scheduled Min-Sum Decoding of LDPC Codes
• Optimum Soft-Output of Autoregressive Detector for Offtrack Interference in LDPC-Coded Perpendicular Magnetic Recording
• Design and Performance of Rate-Compatible Non-binary LDPC Convolutional Codes
• Spatially Coupled Protograph-Based LDPC Codes for Decode-and-Forward in Erasure Relay Channel

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