Power Minimization for Dual- and Triple-Supply Digital Circuits via Integer Linear Programming

概要

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This paper proposes an Integer Linear Programming (ILP)-based power minimization method by partitioning into regions, first, with three different VDDs(PM3V), and, secondly, with two different VDDs(PM2V). To reduce the solving time of triple-VDD case (PM3V), we also proposed a partitioned ILP method(p-PM3V). The proposed method provides 29% power saving on the average in the case of triple-VDD compared to the case of single VDD. Power reduction of PM3V compared to Clustered Voltage Scaling (CVS) was about 18%. Compared to the unpartitioned ILP formulation(PM3V), the partitioned ILP method(p-PM3V) reduced the total solution time by 46% at the cost of additional power consumption within 1.3%.
（社）電子情報通信学会の論文
2009-09-01