Efficient Encoding Architecture for IEEE 802.16e LDPC Codes

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概要

• 論文の詳細を見る

• The weakness of implementation for LDPC encoder is that conventional binary Matrix Vector Multiplier has many clock cycles which lead to limited throughput. In this letter in order to construct efficient architecture, we target on IEEE 802.16e LDPC encoders. Over the standard H matrices with Circulant Permutation Matrices, we propose semi-parallel architecture by using cyclic right shift registers and exclusive-OR instead of complex Matrix Vector Multipliers. Proposed efficient encoder for IEEE 802.16e LDPC satisfies compact size and high throughput.

• （社）電子情報通信学会の論文
• 2008-12-01

著者

• Lee Moon

  Chonbuk National Univ. Jeonju Kor

• Kim Jeong

  Chonbuk National University

• YOO Hyunseuk

  Chonbuk National University

• Yoo Hyunseuk

  Chonbuk National Univ. Kor

• Lee Moon

  Chonbuk National University

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