A Power Grid Optimization Algorithm by Observing Timing Error Risk by IR Drop

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概要

• 論文の詳細を見る

• With the advent of the deep submicron age, circuit performance is strongly impacted by process variations and the influence on the circuit delay to the power-supply voltage increases more and more due to CMOS feature size shrinkage. Power grid optimization which considers the timing error risk caused by the variations and IR drop becomes very important for stable and hi-speed operation of system-on-chip. Conventionally, a lot of power grid optimization algorithms have been proposed, and most of them use IR drop as their object functions. However, the IR drop is an indirect metric and we suspect that it is vague metric for the real goal of LSI design. In this paper, first, we propose an approach which uses the “timing error risk caused by IR drop” as a direct objective function. Second, the critical path map is introduced to express the existence of critical paths distributed in the entire chip. The timing error risk is decreased by using the critical path map and the new objective function. Some experimental results show the effectiveness.

• （社）電子情報通信学会の論文
• 2008-12-01

著者

• Kawakami Yoshiyuki

  Graduate School Of Science And Engineering Ritsumeikan University

• TSUKIYAMA Shuji

  Dept. of Electrical, Electronic, and Communication Eng., Chuo University

• Tsukiyama Shuji

  Dept. Of Eece Chuo University

• Fukui Masahiro

  Dept. Of Vlsi System Design Ritsumeikan University

• TERAO Makoto

  Graduate School of Science and Engineering, Ritsumeikan University

• Terao Makoto

  Graduate School Of Science And Engineering Ritsumeikan University

関連論文

• A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays(Circuit Synthesis,VLSI Design and CAD Algorithms)
• A Power Grid Optimization Algorithm by Observing Timing Error Risk by IR Drop
• Generation of Minimal Separating Sets of a Graph (Special Section on Discrete Mathematics and Its Applications)
• A Power Modeling and Optimization Scheme for Future Ultra Small Size Electric Systems(Low-Power and High-Performance VLSI Circuit Technology,VLSI Technology toward Frontiers of New Market)

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