Logic-Level Analysis of Fault Attacks and a Cost-Effective Countermeasure Design

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概要

• 論文の詳細を見る

• This article analyzes the internal mechanism of fault attacks on microcontrollers and proposes a cost-effective hardware and software countermeasure design policy. Reliable branch operations are essential to DFA-resistant hardware. Our method is based on a logical fault attack simulation to find the minimum set of signals that contribute to faults in the branch operations and is also based on applying partially redundant logic.

• （社）電子情報通信学会の論文
• 2008-07-01

著者

• Okochi Toshio

  Central Research Laborarory Hitachi Ltd.

• KAMINAGA Masahiro

  Dept. of Electrical Eng. and Information Tech., Tohoku-gakuin University

• WATANABE Takashi

  Central Research Laborarory HITACHI Ltd.

• ENDO Takashi

  Central Research Laborarory HITACHI Ltd.

• Kaminaga Masahiro

  Dept. Of Electrical Eng. And Information Tech. Tohoku-gakuin University

関連論文

• Logic-Level Analysis of Fault Attacks and a Cost-Effective Countermeasure Design

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