Concurrent Algorithm and Hardware Implementation for Low-Latency Turbo Decoder Using a Single MAP Decoder

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概要

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• In order to reduce the iterative decoding delay of convolutional turbo codes, this paper presents a concurrent decoding algorithm for the hardware implementation of turbo convolutional decoders. Different than a general turbo code, the hardware turbo decoder based on the proposed algorithm can update the priori information of message for each component code in a bit-by-bit manner as soon as it is generated by the other component code. The two component codes in a turbo code can thus be decoded concurrently, by using a single MAP decoder, subsequently reducing the decoding latency by approximately half while maintaining the bit error rate performance and a comparable hardware complexity, as a general turbo decoder.

• 2010-01-01

著者

• Lu Ya-cheng

  Department Of Electrical Engineering Chang Gung University

• LU Erl-Huei

  Department of Electrical Engineering, Chang Gung University

• Lu Erl‐huei

  Department Of Electrical Engineering Chang Gung University

• Lu Erl-huei

  Department Of Electrical Engineering Chang Gung University

関連論文

• Concurrent Algorithm and Hardware Implementation for Low-Latency Turbo Decoder Using a Single MAP Decoder
• Scalable and Systolic Montgomery Multipliers over GF(2^m)

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