Ultra High Speed CNFET Full-Adder Cell Based on Majority Gates

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概要

• 論文の詳細を見る

• In this paper an ultra high speed CNFET Full-Adder cell is presented. This design generates sum and carry-out signals via majority and majority-not gates which are implemented by CNFET buffer, CNFET inverter and input capacitors. Significant improvement in terms of speed and Power-Delay Product (PDP) is achieved.

• （社）電子情報通信学会の論文
• 2010-06-01

著者

• NAVI Keivan

  Nano-technology and Quantum Computing Lab, Shahid Beheshti University

• SHARIFI Fazel

  Nano-technology and Quantum Computing Lab, Shahid Beheshti University

• MOMENI Amir

  Nano-technology and Quantum Computing Lab, Shahid Beheshti University

• KESHAVARZIAN Peiman

  Nano-technology and Quantum Computing Lab, Shahid Beheshti University

• Navi Keivan

  Nano-technology And Quantum Computing Lab Shahid Beheshti University

• Momeni Amir

  Nano-technology And Quantum Computing Lab Shahid Beheshti University

• Sharifi Fazel

  Nano-technology And Quantum Computing Lab Shahid Beheshti University

• Keshavarzian Peiman

  Nano-technology And Quantum Computing Lab Shahid Beheshti University

関連論文

• Ultra High Speed CNFET Full-Adder Cell Based on Majority Gates
• Ultra High Speed CNFET Full-Adder Cell Based on Majority Gates
• Efficient MRC-Based Residue to Binary Converters for the New Moduli Sets {2^,2^n-1,2^-1} and {2^,2^n-1,2^-1}

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