A Fast-Lock Low-Power Subranging Digital Delay-Locked Loop

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概要

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• A new fast-lock, low-power digital delay-locked loop (DLL) is presented. A subranging searching algorithm is employed to effectively make the loop locked within only four clock cycles. A half-delay circuit is utilized to cut down power consumption. The prototype DLL in a standard 0.13-µm CMOS process operates in the range from 50MHz to 400MHz with four clock cycle lock time and consumes 2.379mW with 1-V supply at 400MHz clock rate. The measured RMS jitter and peak-to-peak jitter at 400MHz are 1.586ps and 16.67ps, respectively. It occupies an active area of 0.038mm2.

• 2010-06-01

著者

• Chen Hsin-shu

  Department Of Electrical Engineering And Graduate Institute Of Electronics Engineering National Taiw

• Lin Jyun-cheng

  Department Of Electrical Engineering And Graduate Institute Of Electronics Engineering National Taiw

関連論文

• A Fast-Lock Low-Power Subranging Digital Delay-Locked Loop

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