A 3-D Packaging Technology with Highly-Parallel Memory/Logic Interconnect

スポンサーリンク

概要

• 論文の詳細を見る
• 2009-12-01

著者

• KURITA Yoichiro

  NEC Electronics Corporation

• SOEJIMA Koji

  NEC Electronics Corporation

• KIKUCHI Katsumi

  NEC Corporation

• TAKAHASHI Masatake

  NEC Corporation

• TAGO Masamoto

  NEC Corporation

• KOIKE Masahiro

  NEC Electronics Corporation

• SHIBUYA Koujirou

  NEC Electronics Corporation

• YAMAMICHI Shintaro

  NEC Corporation

• KAWANO Masaya

  NEC Corporation

関連論文

• A 3-D Packaging Technology with Highly-Parallel Memory/Logic Interconnect
• A 3-D Packaging Technology with Highly-Parallel Memory/Logic Interconnect
• Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link(Analog and Communications,Low-Power, High-Speed LSIs and Related Technologies)
• 60% Power Reduction in Inductive-Coupling Inter-Chip Link by Current-Sensing Technique

スポンサーリンク