Simultaneous Switching Noise Analysis for High-Speed Interface

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概要

• 論文の詳細を見る

• This paper describes the modeling and the analysis methodology to evaluate Simultaneous Switching Noise (SSN) for the combined system of the package with the 4-layer Printed Circuit Board (PCB), which the 64 Simultaneous Switching Outputs (SSOs) were included using a simple IBIS model. Simulation results showed that the ground plane in both package and PCB can be used as the reference to reduce SSN more effectively than the power plane. For the source synchronous timing technique such as used in a DDR SDRAM memory bus in the model shown in this paper, the skew control circuit tequiniqe is easy to apply in the chip design instead of using embedded capacitors in the packages substrate. And also the radiated emission and eye diagram analysis were studied.

• 2009-04-01

著者

• TAKAHASHI Narimasa

  IBM Japan

• KAGAWA Kenji

  ATE Service

• HONDA Yutaka

  ATE Service

• TAKAHASHI Yo

  Shibaura Institute of Technology

関連論文

• Simultaneous Switching Noise Analysis for High-Speed Interface
• Simultaneous Switching Noise Analysis for High-Speed Interface

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