DRAM Controller with a Complete Predictor

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概要

• 論文の詳細を見る

• In the arsenal of resources for computer memory system performance improvement, predictors have gained an increasing role in the past years. They can suppress the latencies when accessing cache or main memory. In paper[1] it is shown how temporal parameters of cache memory access, defined as live time, dead time and access interval could be used for prediction of data prefetching. This paper examines the feasibility of applying an analog technique on controlling of opening/closing DRAM memory rows, with various improvements. The results described herein confirm the feasibility, and allow us to propose a DRAM controller with predictors that not only close the opened DRAM row, but also predict the next row to be opened.

• （社）電子情報通信学会の論文
• 2009-04-01

著者

• STANKOVIC Vladimir

  Faculty of Electronic Engineering

• MILENKOVIC Nebojsa

  Faculty of Electronic Engineering

• Stankovic Vladimir

  Fac. Of Electronic Engineering Nis Zzz

• Milenkovic Nebojsa

  Fac. Of Electronic Engineering Nis Zzz

関連論文

• DDR3 SDRAM with a Complete Predictor
• DDR3 SDRAM with a Complete Predictor
• DRAM Controller with a Complete Predictor

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