Suppression of Gate Depletion in p+ Polysilicon Gated Sub-40nm PMOS Devices by Laser Thermal Process

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概要

• 論文の詳細を見る
• 2004-09-15

著者

• Yamamoto T.

  Fujitsu Laboratories Ltd.

• Talwar S.

  Ultratech Inc.

• Kase M.

  Fujitsu Ltd.

• KUBO T.

  Fujitsu Ltd.

• OKABE K.

  Fujitsu Ltd.

• SUKEGAWA T.

  Fujitsu Ltd.

• WANG Y.

  Ultratech Inc.

• LIN T.

  Ultratech Inc.

関連論文

• B-10-172 40 GHz Optical Clock Extraction from 160 Gbit/s Data Signals Using PLL-based Clock Recovery
• Suppression of Gate Depletion in p+ Polysilicon Gated Sub-40nm PMOS Devices by Laser Thermal Process
• Tapered Thickness Waveguide Integrated BH MQW Lasers

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