Concurrent Symbol Processing Capable VLSI Architecture for Bit Plane Coder of JPEG2000(Image Processing and Multimedia Systems, <Special Section>Recent Advances in Circuits and Systems)

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概要

• 論文の詳細を見る

• JPEG2000 image compression standard is designed to cater the needs of a large span of applications including numerous consumer products. However, its use is restricted due to the high hardware cost involved in its implementation. Bit Plane Coder (BPC) is the main resource intensive component of JPEG2000. Its throughput plays a key role in deciding the overall throughput of a JPEG2000 encoder. In this paper we present the algorithm and parallel pipelined VLSI architecture for BPC which processes a complete stripe-column concurrently during every pass. The hardware requirements and the critical path delay of the proposed technique are compared with the existing solutions. The experimental results show that the proposed architecture has 2.6 times greater throughput than existing architectures, with a comparatively small increase in hardware cost.

• 一般社団法人電子情報通信学会の論文
• 2005-08-01

著者

• Gupta Amit

  Faculty Of Electrical Engineering At Unsw

• Nooshabadi Saeid

  Faculty Of Electrical Engineering At Unsw

• TAUBMAN David

  Faculty of Electrical Engineering at UNSW

関連論文

• Concurrent Symbol Processing Capable VLSI Architecture for Bit Plane Coder of JPEG2000(Image Processing and Multimedia Systems, Recent Advances in Circuits and Systems)

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