Boundary Scan Test Scheme for IP Core Identification via Watermarking(Programmable Logic, VLSI, CAD and Layout, <Special Section>Recent Advances in Circuits and Systems-Part 1)

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概要

• 論文の詳細を見る

• This paper proposes a novel boundary scan test scheme for intellectual property (IP) core identification via watermarking. The core concept is embedding a watermark identification circuit (WIC) and a test circuit into the IP core at the behavior design level. The procedure depends on current IP-based design flow. This scheme can detect the identification of the IP provider without the need to examine the microphotograph after the chip has been manufactured and packaged. This scheme can successfully survive synthesis, placement, and routing and identify the IP core at various design levels. Experimental results have demonstrated that the proposed approach has the potential to solve the IP identification problem.

• 社団法人電子情報通信学会の論文
• 2005-07-01

著者

• FAN Yu

  Department of Biochemistry & Molecular Biology, Institute of Basic Medical Sciences, Chinese Academy

• Fan Yu

  Department Of Electrical Engineering And Graduate Institute Of Electronics Engineering National Taiw

• Tsao Hen

  Department Of Electrical Engineering And Graduate Institute Of Communication Engineering National Ta

• Tsao Hen

  Department Of Electrical Engineering And Graduate Institute Of Electronics Engineering National Taiw

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