CMOS Radio Design for Complete Single Chip GPS SoC(Analog, <Special Section>Low-Power LSI and Low-Power IP)

スポンサーリンク

概要

• 論文の詳細を見る

• A GPS radio design for a complete single chip GPS receiver using 0.18-μm CMOS is presented. The complete single chip GPS receiver satisfies several key requirements for mobile applications, such as compactness, low power, and high sensitivity. The radio part, including the RF front end, the RF/IF PLLs, and IF functions, occupies 2.0×2.3 mm in a total chip area of 6.3×6.3 mm. It is fabricated using 0.18-μm CMOS technology utilizing MIM capacitors. The radio part operates within a 1.6 to 2.0V supply voltage range and consumes 27 mW at 1.8V. The whole GPS SoC consumes 57 mW for a fully functional chip and provides a high sensitivity of -152 dBm. The radio design features countermeasures against substrate coupling noise from the digital part.

• 社団法人電子情報通信学会の論文
• 2005-04-01

著者

• Suzuki Norihito

  Sony Corporation

• KATAKURA Masayuki

  Sony Corporation

• KADOYAMA Takahide

  Sony Corporation

関連論文

• A Study on Effect of Integrator Non-Linearity on Performance Degradation of * Δ Modulator
• CMOS Radio Design for Complete Single Chip GPS SoC(Analog, Low-Power LSI and Low-Power IP)
• FOREWORD

スポンサーリンク