Analysis and Design of Multistage Low-Phase-Noise CMOS LC-Ring Oscillators(General Fundamentals and Boundaries)

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概要

• 論文の詳細を見る

• A novel CMOS LC oscillator architecture combining an LC tuned oscillator and a ring structure is presented as a new design topology to deliver improved phase noise for multiphase applications. The relative enhancement in the phase noise is estimated using a linear noise modeling approach. A three-stage LC-ring oscillator fabricated in a 0.6mm CMOS technology achieves measured phase noise of -132dBc/Hz at 600kHz offset from a 900MHz carrier and dissipates 20mW with a 2.5V power supply.

• 社団法人電子情報通信学会の論文
• 2005-04-01

著者

• Kim Beomsup

  Berkana Wireless Inc.

• LIM Jaesang

  Korea Advanced Institute of Science and Technology

• KIM Jaejoon

  MagnaChip Semiconductor Ltd.

• Lim Jaesang

  Korea Advanced Inst. Of Sci. And Technol. Daejon Kor

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• Analysis and Design of Multistage Low-Phase-Noise CMOS LC-Ring Oscillators(General Fundamentals and Boundaries)
• Digital Calibration Techniques for Pipelined ADCs(Analog Signal Processing)

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