Unified Phase Compiler by Use of 3-D Representation Space(<Special Section>Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)

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概要

• 論文の詳細を見る

• A novel unified phase compiler framework for embedded VLIWs and DSPs is shown. In this compiler, a given program is represented in 3-D representation space, which enables quantitatively estimating required resources and elapsed time. Transformation of a 3-D representation graph that corresponds to a code optimization method for a specific processor architecture is also proposed. The proposal compiler and the code optimization methods are compared with an ordinary compiler in terms of their generated codes. The results demonstrate their effectiveness.

• 社団法人電子情報通信学会の論文
• 2005-04-01

著者

• Sugino Nobuhiko

  Tokyo Inst. Technol. Yokohama‐shi Jpn

• MIYOSHI Takefumi

  Tokyo Institute of Technology

• Miyoshi Takefumi

  Tokyo Inst. Technol. Yokohama‐shi Jpn

関連論文

• Memory Allocation and Code Optimization Methods for DSPs with Indexed Auto-Modification(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
• Unified Phase Compiler by Use of 3-D Representation Space(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)

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