Super-high Speed, Accuracy, and Modularized Residue Number System based on Redundant Binary Representation

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概要

• 論文の詳細を見る

• The multiplier and divider used for specific hardware of public key cryptosystem arithmetic are constructed from many adders and subtractors to improve the accuracy of the key. However, with the increase of accuracy, the propagation delay problem becomes unavoidable. Although some paper have proposed that a divider using redundant binary representation is effective to cope with this problem, no considerations were given to the problems of rounding error and accuracy of the remainder. This paper proposes a method, based on inherent bit sliced architecture, that can cope with these problems and that is expandable to any level of accuracy. It is expected to make it applicable to hardware for public key cryptosystem that can be flexible in coping with the expansion of the key string and the variable length key.

• 社団法人 電気学会の論文
• 2005-06-01

著者

• Kasahara Hiroshi

  Tokyo Denki University

• Abe Kazuhiro

  Fujitsu Ltd.

• NAKAMURA Tsugio

  Department of Information network, Kokusai Junior College

• FUYUTSUME Narito

  The School of Information Environment, Tokyo Denki University

• KASAHARA Hiroshi

  The School of Information Environment, Tokyo Denki University

• TANAKA Teruo

  The Department of Electrical Engineering, Tokyo Denki University

• Nakamura Tsugio

  Kokusai Junior College

• Fuyutsume Narito

  Tokyo Denki University

• Tanaka Teruo

  The Department Of Electrical Engineering Tokyo Denki University

関連論文

• Usefulness of Impedance Cardiography and Pulse Study for the Evaluation of the Pharmacological Action of the Depressants
• Super-high Speed, Accuracy, and Modularized Residue Number System based on Redundant Binary Representation
• C-12-10 Hardware Implementation of Elliptic Curve Cryptosystem Adaptive to Infinite Key Length

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