A Double-Level-V_<th> Select Gate Array Architecture for Multilevel NAND Flash Memories
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概要
- 論文の詳細を見る
- 1996-07-25
著者
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Tanaka Tomoharu
The Microelectronics Engineering Laboratory Toshiba Corporation
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TAKEUCHI Ken
the Microelectronics Engineering Laboratory, Toshiba Corporation
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NAKAMURA Hiroshi
the Microelectronics Engineering Laboratory, Toshiba Corporation
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Takeuchi Ken
The Microelectronics Engineering Laboratory Toshiba Corporation