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Tokyo Univ. Sci. Noda‐shi Jpn | 論文
- Structured Triacylglycerol Containing Medium-Chain Fatty Acids in sn-1(3) Facilitates the Absorption of Dietary Long-Chain Fatty Acids in Rats
- Lymphatic Transport of Dietary Cholesterol Oxidation Products, Cholesterol and Triacylglycerols in Rats(Food & Nutrition Science)
- Lowering the Error Floors of Irregular LDPC Code on Fast Fading Environment with Perfect and Imperfect CSIs(Wireless Communication Technologies)
- Decoding Algorithms Based on Oscillation for Low-Density Parity Check Codes(Coding Theory)
- Companding System Based on Time Clustering for Reducing Peak Power of OFDM Symbol in Wireless Communications(Multi-dimensional Mobile Information Networks)
- A Sign Selection Method of Orthogonal Variable Spreading Factor Code for Peak Power Reduction in Multi-Rate OFCDM Systems(Wireless Communication Technologies)
- Criterion for Reducing Error Rate Degradation by Nonlinear Amplifier for Multicarrier Transmission(Wireless Communication Technologies)
- Frequency Offset Compensation with MMSE-MUD for Multi-Carrier CDMA in Quasi-Synchronous Uplink(Wireless Communication Technology)
- FPGA-Based Reconfigurable Adaptive FEC(System Level Design)(VLSI Design and CAD Algorithms)
- Evaluation of Asymmetric TDD Systems Employing AMC and HARQ by Considering MCS Selection Errors(Wide Band Systems)
- B-5-3 Throughput Evaluation on Asymmetric Slot Allocations in TDD Scheme with Control Loop Delay of AMC in Downlink
- A Study on Higher Order Differential Attack of KASUMI(Symmetric Cryptography,Cryptography and Information Security)
- Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures
- Selective Low-Care Coding : A Means for Test Data Compression in Circuits with Multiple Scan Chains(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier (System LSIs and Microprocessors, VLSI Design Technology in the Sub-100nm Era)
- A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition(Programmable Logic, VLSI, CAD and Layout, Recent Advances in Circuits and Systems-Part 1)
- Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
- High-Level Power Optimization Based on Thread Partitioning(System Level Design)(VLSI Design and CAD Algorithms)
- A Hardware/Software Cosynthesis Algorithm for Processors with Heterogeneous Datapaths(Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
- A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions(Design Methodology)(VLSI Design and CAD Algorithms)