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School of Fundamental Science and Engineering Waseda university | 論文
- サービスの開始と終了を考慮したWebトラヒックの非定常Poisson過程によるモデル化について(トラヒック解析・制御)
- 多端子情報理論に基づくセンサネットワークのモデル化と信頼度評価
- バースト消失訂正とLDPC符号に関する一考察
- 多端子情報理論に基づくセンサネットワークのモデル化と信頼度評価
- A Note on the ε-Overflow Probability of Lossless Codes(Information Theory)
- A Note on the overflow probability of lossless codes
- ランプ型鍵事前配布方式における参加者の記憶容量の下界と最適な構成法について (情報理論)
- 線形計画法に基づいたファクターグラフ上の推論アルゴリズムに関する一考察 (情報理論)
- 不均一誤り訂正符号を用いた直積ファイルのディスク配置 (情報理論)
- FPGA-Based Reconfigurable Adaptive FEC(System Level Design)(VLSI Design and CAD Algorithms)
- Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures
- Selective Low-Care Coding : A Means for Test Data Compression in Circuits with Multiple Scan Chains(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier (System LSIs and Microprocessors, VLSI Design Technology in the Sub-100nm Era)
- A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition(Programmable Logic, VLSI, CAD and Layout, Recent Advances in Circuits and Systems-Part 1)
- Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
- High-Level Power Optimization Based on Thread Partitioning(System Level Design)(VLSI Design and CAD Algorithms)
- A Hardware/Software Cosynthesis Algorithm for Processors with Heterogeneous Datapaths(Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
- A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions(Design Methodology)(VLSI Design and CAD Algorithms)
- A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions(Simulation Acceletor)(VLSI Design and CAD Algorithms)
- A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions