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Department of Computer Engineering, Yeungnam University | 論文

• Design of State Estimator for Discrete-Time Neural Networks : Delay-Independent Approach(General)
• Torus Ring : Improving Interconnection Network Performance by Modifying Hierarchical Ring(Computer Systems)
• The Impact of Branch Direction History Combined with Global Branch History in Branch Prediction(Computer Systems)
• Throttling Capacity Sharing Using Life Time and Reuse Time Prediction in Private L2 Caches of Chip Multiprocessors
• Bypass Extended Stack Processing for Anti-Thrashing Replacement in Shared Last Level Cache of Chip Multiprocessors
• Write Avoidance Cache Coherence Protocol for Non-volatile Memory as Last-Level Cache in Chip-Multiprocessor

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