Goto Shigeki | Department of Computer Science and Engineering Waseda University
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概要
Department of Computer Science and Engineering Waseda University | 論文
- A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit
- FPGA-Based Reconfigurable Adaptive FEC(System Level Design)(VLSI Design and CAD Algorithms)
- Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures
- Fast Scheduling and Allocation Algorithms for Entropy CODEC (Special Issue on Synthesis and Verification of Hardware Design)
- A Circuit Partitioning Algorithm with Path Delay Constraints for Multi-FPGA Systems (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)