JOU Jing-Yang | the Department of Electronics Engineering, National Chiao-Tung University
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- the Department of Electronics Engineering, National Chiao-Tung Universityの論文著者
the Department of Electronics Engineering, National Chiao-Tung University | 論文
- Efficient Vector Compaction Methods for Power Estimation with Consecutive Sampling Techniques(VLSI Design Technology and CAD)
- An Efficient Power Model for IP-Level Complex Designs (VLSI Design Technology and CAD)