YOSHIMURA Masayoshi | Corporate Development Division, Semiconductor Company, Matsushita Electric Industrial Co., Ltd.
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- 同名の論文著者
- Corporate Development Division, Semiconductor Company, Matsushita Electric Industrial Co., Ltd.の論文著者
Corporate Development Division, Semiconductor Company, Matsushita Electric Industrial Co., Ltd. | 論文
- Novel DFT Strategies Using Full/Partial Scan Designs and Test Point Insertion to Reduce Test Application Time(Special Section on VLSI Design and CAD Algorithms)
- Partial Scan Design Methods Based on n-Fold Line-Up Structures and the State Justification of Pure Load/Hold Flip-Flops(Special Issue on Test and Diagnosis of VLSI)
- Performance Estimation at Architecture Level for Embedded Systems(Special Section on VLSI Design and CAD Algorithms)