O'uchi Shinichi | Silicon Nanoscale Device Group, Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology (AIST), 2-13 Tsukuba Central, Tsukuba, Ibaraki 305-8568, Japan

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• 同名の論文著者
• Silicon Nanoscale Device Group, Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology (AIST), 2-13 Tsukuba Central, Tsukuba, Ibaraki 305-8568, Japanの論文著者

Silicon Nanoscale Device Group, Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology (AIST), 2-13 Tsukuba Central, Tsukuba, Ibaraki 305-8568, Japan | 論文

• Minimization of Gate-Induced Drain Leakage by Controlling Gate Underlap Length for Low-Standby-Power Operation of 20-nm-Level Four-Terminal Silicon-on-Insulator Fin-Shaped Field Effect Transistor

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