Yamaguchi M | Tokyo Univ. Sci. Noda‐shi Jpn
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概要
Tokyo Univ. Sci. Noda‐shi Jpn | 論文
- Decoding Algorithms Based on Oscillation for Low-Density Parity Check Codes(Coding Theory)
- FPGA-Based Reconfigurable Adaptive FEC(System Level Design)(VLSI Design and CAD Algorithms)
- Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures
- Selective Low-Care Coding : A Means for Test Data Compression in Circuits with Multiple Scan Chains(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier (System LSIs and Microprocessors, VLSI Design Technology in the Sub-100nm Era)