KOUYAMA Shin'ichi | Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto Univers
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概要
- 同名の論文著者
- Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto Universの論文著者
Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto Univers | 論文
- A 90nm 48×48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations(Low-Power and High-Performance VLSI Circuit Technology,VLSI Technology toward Frontiers of New Market)
- A 90nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations(Digital,Low-Power, High-Speed LSIs and Related Technologies)
- A Memory-Based Parallel Processor for Vector Quantization:FMPP-VQ (Special Issue on New Concept Device and Novel Architecture LSIs)
- A 65 nm Complementary Metal--Oxide--Semiconductor 400 ns Measurement Delay Negative-Bias-Temperature-Instability Recovery Sensor with Minimum Assist Circuit
- Impact of Body-Biasing Technique on Random Telegraph Noise Induced Delay Fluctuation