WATANABE Takahiro | the Department of Computer Science and Systems Engineering, Faculty of Engineering, Yamaguchi Univer

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概要

関連著者

NAKAMURA Tadao
the Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohok
Watanabe T
School Of Administration And Informatics University Of Shizuoka
Matsubara Hiroyuki
Department Of Computer And Mathematical Sciences Graduate School Of Information Sciences Tohoku Univ
Matsubara Hiroyuki
Department Of Physics Faculty Of Science Shizuoka University.
Nakamura Toshio
Department Of Computer And Mathematical Sciences Graduate School Of Information Sciences Tohoku Univ
MATSUBARA Hiroyuki
the Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohok
WATANABE Takahiro
the Department of Computer Science and Systems Engineering, Faculty of Engineering, Yamaguchi Univer
Watanabe T
Department Of Computer Science And Systems Engineering Faculty Of Engineering Yamaguchi University

著作論文

A Clocking Scheme for Lowering Peak-Current in Dynamic Logic Circuits (Special Issue on Low-power LSIs and Technologies)

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