De Jonghe | PHILIPS Semiconductors
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概要
PHILIPS Semiconductors | 論文
- Highly scalable and WF-tunable Ni(Pt)Si / SiON TOSI-gate CMOS devices obtained in a CMP-less integration scheme
- Using MASTAR as a Pre-SPICE Model Generator for Early Technology Assessment and Circuit Simulation
- 45nm Conventional Bulk and "Bulk+" Architectures for Low-Cost GP/LP Applications
- Effect of Process Induced Strain in 35nm FDSOI Devices with Ultra-Thin Silicon Channels
- Mechanical and Electrical Analysis of Strained Liner Effect in 35 nm Fully Depleted Silicon-on-Insulator Devices with Ultra Thin Silicon Channels