Nakamura Hiroyuki | Center for Microelectronic Systems, Kyushu Institute of Technology, 680-4 Kawazu, Iizuka, Fukuoka 820-8502, Japan
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- Nakamura Hiroyukiの詳細を見る
- 同名の論文著者
- Center for Microelectronic Systems, Kyushu Institute of Technology, 680-4 Kawazu, Iizuka, Fukuoka 820-8502, Japanの論文著者
Center for Microelectronic Systems, Kyushu Institute of Technology, 680-4 Kawazu, Iizuka, Fukuoka 820-8502, Japan | 論文
- Dynamic Strain and Chip Damage during Ultrasonic Flip Chip Bonding
- Low-Voltage-Signaling CMOS Receiver with Dynamic Threshold Control
- Increased Emission Efficiency of Gated Cold Cathode with Carbonic Nano-Pillars
- Pyramid Bumps for Fine-Pitch Chip-Stack Interconnection
- Pyramid Bumps for Fine-Pitch Chip-Stack Interconnection