Kawamura Akira | High-Technology Research Center and Faculty of Engineering, Kansai University, 3-3-35 Yamate-cho, Suita, Osaka 564-8680, Japan

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High-Technology Research Center and Faculty of Engineering, Kansai University, 3-3-35 Yamate-cho, Suita, Osaka 564-8680, Japan | 論文

• Simulation Models for Silicon-on-Insulator Tunneling-Barrier-Junction Metal–Oxide–Semiconductor Field-Effect Transistor and Performance Perspective

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