Pinch-Off Voltage Lowering in Polycrystalline Silicon Thin-Film Transistors

概要

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Pinch-off voltage ($V_{\text{p}}$) lowering phenomenon in the output characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) is reported and investigated by measurement and device simulation. As the trap density increases, the observed $V_{\text{p}}$ becomes smaller than the ideal $V_{\text{p}}$ while maintaining a linear relationship with the gate--source voltage ($V_{\text{gs}}$). The device simulation analysis revealed two mechanisms for $V_{\text{p}}$ lowering. One is current saturation due to the increase in onset gate--drain voltage ($V_{\text{gd}}$), causing the drain region to become highly resistive, which originates from the gradual increase in surface potential with $V_{\text{gs}}$. This is interpreted as an expansion of the conventional pinch-off concept. The other is the current limitation, controlled by grain boundary (GB) and intragrain conductance at the drain edge, which is peculiar to poly-Si TFTs. On the basis of the above analysis, a GB-conductance-limited carrier transport model is proposed. Its good agreement with the measurements suggests the suitability of this model for describing $V_{\text{p}}$ lowering.
2011-01-25