Analysis of Gate Delay Scaling in In0.7Ga0.3As-Channel High Electron Mobility Transistors
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概要
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The intrinsic and the parasitic gate delay of In0.7Ga0.3As-channel high electron mobility transistors (HEMTs) are analyzed. In this paper, we extract the intrinsic parameters of sub-100-nm gate pseudomorphic InGaAs channel HEMTs and estimate the intrinsic and parasitic gate delay. We discuss how the intrinsic and parasitic gate delay are affected by scaling of the gate length and we estimate the parasitic gate capacitance from this gate delay analysis. We also compare the result of the gate delay analysis with lattice-matched InGaAs-channel HEMTs to examine the effect of use of the pseudomorphic InGaAs channel in the gate delay.
- 2009-04-25
著者
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Otsuji Taiichi
Research Institute Of Electrical Communication Tohoku University
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Suemitsu Tetsuya
Research Institute Of Electrical Communication Tohoku University
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DEL ALAMO
Massachusetts Institute of Technology
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del Alamo
Massachusetts Institute of Technology, Cambridge, MA 02139, U.S.A.
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Suemitsu Tetsuya
Research Institute of Electrical Communication, Tohoku University, Sendai 980-8577, Japan
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Kim Dae-Hyun
Massachusetts Institute of Technology, Cambridge, MA 02139, U.S.A.
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Fukuda Shunsuke
Research Institute of Electrical Communication, Tohoku University, Sendai 980-8577, Japan
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Otsuji Taiichi
Research Institute for Electrical Communication, Tohoku University, Sendai 980-8577, Japan
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Suemitsu Tetsuya
Research Institute of Electrical Communication (RIEC), Tohoku University, Sendai 980-8577, Japan
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