Mitigation of Complementary Metal–Oxide–Semiconductor Variability with Metal Gate Metal–Oxide–Semiconductor Field-Effect Transistors

概要

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Variability due to Fermi level pinning at polycrystalline silicon gate grain boundary is examined as an additional source of intrinsic parameter fluctuation. Threshold voltage ($V_{\text{t}}$) variation with metal gate to avoid the variation is found to be mitigated with the measurement of n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) with an identical process except gate stack. The statistical variation of intrinsic gate delay and static noise margin of the 6 transistors static random access memory (SRAM) cell is predicted for future technology nodes using Monte Carlo circuit simulation with a process/physics-based compact model. It is found that the variability can be suppressed by ${\sim}35$% with adopting metal gate for 32 nm technology node.
2009-04-25