The Impact of Technology Scaling for RF Complementary Metal–Oxide–Semiconductor
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概要
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Optimum methodology of scaling for RF complementary metal–oxide–semiconductor (CMOS) has been studied by investigating cutoff frequency ($ f_{\text{T}}$), maximum oscillation frequency ($ f_{\text{max}}$), RF noise, and linearity with simulations and experiments. In the case of MOS field effect transistors (MOSFETs) with multi-finger structure, $ f_{\text{max}}$ and noise figure show trade-off between gate resistance and gate-bulk capacitance because of the existence of gate area for contact. By optimizing finger length for each technology, high $ f_{\text{max}}$ and low minimum noise figure are realized with little sacrifice of $ f_{\text{T}}$. In terms of the linearity, optimized gate width scaling is important. Stress enhancement technique is confirmed to be beneficial also in RF performance because of the enhancement of mobility which results in improvement of $ f_{\text{T}}$ and other RF characteristics. It should be concluded that the improvement of RF characteristics is expected with scaling down the devices by adding gate width and finger length as the significant scaling parameters.
- 2009-01-25
著者
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Matsuoka Fumitomo
System LSI Division, Toshiba Corporation, 580-1 Horikawa-cho, Saiwai-ku, Kawasaki 212-8520, Japan
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Morifuji Eiji
System LSI Division, Toshiba Corporation, 580-1 Horikawa-cho, Saiwai-ku, Kawasaki 212-8520, Japan
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Iwai Masaaki
System LSI Division, Toshiba Corporation, 580-1 Horikawa-cho, Saiwai-ku, Kawasaki 212-8520, Japan
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Kimijima Hideki
System LSI Division, Toshiba Corporation, 580-1 Horikawa-cho, Saiwai-ku, Kawasaki 212-8520, Japan
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Kojima Kenji
System LSI Division, Toshiba Corporation, 580-1 Horikawa-cho, Saiwai-ku, Kawasaki 212-8520, Japan
関連論文
- Optimization of Stress Memorization Technique for 45 nm Complementary Metal–Oxide–Semiconductor Technology
- The Impact of Technology Scaling for RF Complementary Metal–Oxide–Semiconductor