Evaluation of Gate Oxide Damage Caused by Ionization Magnetron Sputtering
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概要
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An unbalanced magnet (UM) is commonly employed in ionization magnetron sputtering (IMS) in order to increase the ionization rates of sputtering species. In this paper, sputtering using an UM is compared with that using a balanced magnet (BM) during the deposition of Ti thin layers. Ti layers were fabricated on the top of polycrystalline silicon (poly-Si) gate electrodes of antenna metal oxide semiconductor (MOS) capacitors with various thicknesses of gate SiO2 layers ranging from 25 to 80 Å, and the durability of the gate SiO2 layers was monitored by current–voltage ($I$–$V$) measurements. It was found that the MOS capacitors with thin SiO2 layers fabricated with the UM were much more damaged than those fabricated with the BM. This characteristic became more marked for thinner SiO2 layers. Its origin was investigated by monitoring the current injected from the plasma to the substrate using a specially designed electrical configuration, and was explained as follows. Electrons are carried toward substrates by curvature drift originating from the diverging magnetic field perpendicular to the substrate. This causes the accumulation of electrons on the gate SiO2 thin layers where the diverging magnetic field is developed at the beginning of discharge, i.e., before the uniform Ti deposition starts to occur. Consequently, the accumulated electrons break the gate SiO2 layer. These results suggest that a new design of magnetic fields for the UM is needed so that the magnetic field does not reach the substrate. It is particularly important to keep the diverging magnetic fields away from the substrates at the beginning of discharge.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2007-11-15
著者
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Hayase Shuzi
Graduate School Of Life Science And System Engineering Kyushu Institute Of Technology
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Iyanagi Katsumi
Process Research Center, Corporate Manufacturing Engineering Center, Toshiba Corporation, 33 Shin-Isogo-cho, Isogo-ku, Yokohama 235-0017, Japan
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Fukuhara Jota
Process Engineering Group II, Manufacturing Engineering Department, Yokkaichi Operations, Semiconductor Company, Toshiba Corporation, 800 Yamanoisshiki-cho, Yokkaichi, Mie 512-8550, Japan
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Matsunaka Shigeki
Process Research Center, Corporate Manufacturing Engineering Center, Toshiba Corporation, 33 Shin-Isogo-cho, Isogo-ku, Yokohama 235-0017, Japan
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