Comparison of Trimming Techniques for Sub-Lithographic Silicon Structures

概要

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The trimming of electron beam features is investigated to explore the limits of this scaling technique for the fabrication of nano-scale devices. The semiconductor industry, in particular, needs features below 50 nm, e.g., for extremely small gates for future technology nodes. In addition, sub-lithographic structures are required for other device concepts, such as the fin-type field effect transistor (FinFET). The trimming of very thin layers of calixarene, an organic resist material, as well as an oxide-like resist (hydrogen-silesquioxane) were investigated and extremely small feature sizes, well below 10 nm, were achieved. Resist structures down to 4 nm in width and silicon features of about 8 nm have been successfully fabricated. Different trimming procedures utilizing plasma resist trimming, etching of Tetraethylorthosilicate (TEOS) hard-masks in hydrofluoric acid (HF) and sacrificial oxidation were compared and, for the first time, a comprehensive study of these techniques applied to sub-10 nm-structuring is presented. In summary, results prove the potential of the trimming procedures investigated here, each of which has specific applications.
Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
2006-06-30