Stress Analyses during Chemical Mechanical Planarization Processing with Cu/Porous Low-$k$ Structures of LSI Devices

概要

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Porous low-$k$ materials are required for the construction of 45-nm-node LSI devices. However, the extremely low Young's modulus values of these materials result in the stress corrosion cracking (SCC) of the Cu interconnects during chemical mechanical planarization (CMP). We performed finite element method analyses of the stress at each step during the CMP. The results showed that the horizontal tensile stress was especially concentrated at the edges of the isolated fine wiring, and that higher tensile stresses appeared at the step of the barrier CMP. Moreover, the maximum values of the tensile stress increased with a decrease in Young's modulus in the low-$k$ films. The cause of the horizontal tensile stress was the downward CMP pressure, which indented the low-$k$ films. These results suggest that CMP with a lower downward pressure and an LSI structure with a Cu dummy pattern were effective for avoiding SCC.
Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
2005-12-15