Gap States Induced by Local Oxidation of Silicon in Iron-Contaminated p on p+ Epitaxial Silicon Wafers

スポンサーリンク

概要

• 論文の詳細を見る

• Heavily doped areas and lattice strains in device structures can provide effective traps for metals and compete with intentionally introduced gettering sites for impurities. In this study, the effect of device structures on Fe gettering by p+ substrates was investigated by reverse current measurements and deep level transient spectroscopy (DLTS) of n+–p junction diodes. A significant improvement in the gettering efficiency was achieved by optimizing the cooling rate in annealing. DLTS detected the gap states, which act as minority carrier traps, in the wafers without optimization of annealing conditions. The gap states correlated to the perimeter length of n+–p junctions, which were defined by local oxidation of silicon (LOCOS). The leakage current and the density of gap states were greatly reduced by optimizating the cooling rate. We suggest that the Fe atoms gettered by lattice strain due to LOCOS generate the gap states, and that these gap states are the origin of excess leakage current.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2005-12-15

著者

• Horikawa Mitsuhiro

  Technology and Development Office, Elpida Memory Inc., 7-10 Yoshikawa Kogyo Danchi, Higashi-Hiroshima, Hiroshima 739-0198, Japan

関連論文

• Gap States Induced by Local Oxidation of Silicon in Iron-Contaminated p on p+ Epitaxial Silicon Wafers

スポンサーリンク