Simulation of Photoresist Thermal Flow Process with Viscous Flow Model
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概要
- 論文の詳細を見る
The photoresist (PR) thermal flow process is to enhance the resolution of lithography for the patterning of sub-200 nm-diameter contact holes as the required critical dimension (CD) approaches the physical limits of conventional lithography. It is difficult to predict the results of the application of this process, so we develop a new viscous PR flow model, which is verified to be applicable for various PRs from experimental results and is applied to the optimization of the layout design and process parameters. Using the model and simulation, we demonstrate the close agreement between the predicted and obtained results using with vertical scanning electron microscope (VSEM) to study the top corner rounding profile of a PR, and present a method for predicting the effect of changes in the dominant variables such as contact diameter, surrounding bulk density, and temperature. This model is also integrated with a lithography simulator. The layout design and process conditions for patterns with various contact diameters are optimized using our new methodology. The viscous flow model linked to the lithography simulator can be effectively used for predicting the contact patterning process and optimizing the layout, as well as, for analyzing defects.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2004-09-15
著者
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Chung Won-young
Cae Team Semiconductor R&d Center Samsung Electronics
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Kim Hyun-woo
Process Development Team Semiconductor R&d Center Samsung Electronics
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Kong Jeong-taek
Cae Team Semiconductor R&d Center Samsung Electronics
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Yoon Jin-young
Process Development Team Semiconductor R&d Center Samsung Electronics
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Park Young-kwan
Cae Team Semiconductor R&d Center Samsung Electronics
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Kim Tai-kyung
Cae Team Semiconductor R&d Center Samsung Electronics
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Kim Hyun-Woo
Process Development Team, Semiconductor R&D Center, Samsung Electronics, San #24, Nongseo-Ri, Giheung-Eup, Yongin-City, Gyeonggi-Do 449-711, Korea
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Kong Jeong-Taek
CAE Team, Semiconductor R&D Center, Samsung Electronics, San #24, Nongseo-Ri, Giheung-Eup, Yongin-City, Gyeonggi-Do 449-711, Korea
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Chung Won-Young
CAE Team, Semiconductor R&D Center, Samsung Electronics, San #24, Nongseo-Ri, Giheung-Eup, Yongin-City, Gyeonggi-Do 449-711, Korea
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Park Young-Kwan
CAE Team, Semiconductor R&D Center, Samsung Electronics, San #24, Nongseo-Ri, Giheung-Eup, Yongin-City, Gyeonggi-Do 449-711, Korea
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Lee Yero
CAE Team, Semiconductor R&D Center, Samsung Electronics, San #24, Nongseo-Ri, Giheung-Eup, Yongin-City, Gyeonggi-Do 449-711, Korea
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Kim Tai-Kyung
CAE Team, Semiconductor R&D Center, Samsung Electronics, San #24, Nongseo-Ri, Giheung-Eup, Yongin-City, Gyeonggi-Do 449-711, Korea
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