Influence of Field-Induced Drain on the Characteristics of Poly-Si Thin-Film Transistor using a Self-Aligned Double Spacer Process

概要

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The electric characteristics of field-induced drain (FID) poly-Si thin-film transistors (poly-Si TFT) with an independently biased self-aligned sub-gate using a double space process are investigated. The on/off current ratio of this FID TFT is approximately $9.3\times 10^{7}$ and the off-state leakage current is 200 times lower than that of the conventional TFT and 60 times lower than that of the LDD TFT at $V_{\text{SG}}=V_{\text{DS}}=5$ V. The self-aligned double spacer process can remove the sub-gate misalignment error and the length of the sub-gate can be easily controlled by the poly-Si thickness and a hard mask. In particular, the use of the dual hard mask can realize a long sub-gate without thick sub-gate poly-Si (${>}500$ nm). The optimum sub-gate voltage is about 5 V and the optimum effective sub-gate length is between 200 nm and 300 nm in these FID TFTs.
Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
2004-03-15