Double-Recessed 0.1-μm-Gate InP HEMTs for 40 Gbit/s Optical Communication Systems

概要

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We have developed a double-recessed 0.1-μm-gate InP-based high electron mobility transistor (DR-HEMT). In this double-recessed-gate structure, the outer-recessed width and the inner-recessed depth are very important in terms of the device characteristics. In order to suppress the maximum electric field strength within the channel region and to reduce the source resistance ($R_{\text{s}}$), we have performed a device simulation and have obtained the optimum double-recessed gate structure. The DR-HEMT shows a good transconductance over drain conductance gain ($g_{\text{m}}/g_{\text{d}}$) of 26 and a high maximum oscillation frequency ($f_{\text{max}}$) of 351 GHz because of the improved $g_{\text{d}}$ with a small $R_{\text{s}}$. The propagation delay ($t_{\text{pd}}$) of a source-coupled field effect transistor logic (SCFL) inverter implemented by DR-HEMTs is as fast as 5.8 ps/gate. We have applied the DR-HEMT technology to a static 1/2 frequency divider and obtained stable operation up to 43 GHz.
INSTITUTE OF PURE AND APPLIED PHYSICSの論文
2003-04-15