Field-Shield Trench Isolation with Self-Aligned Field Oxide
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概要
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A novel fabrication technique for submicrometer trench isolation is proposed. This features a phosphorus-doped polysilicon field shield filled into the trench and a thick isolation oxide formed on polysilicon by impurity-enhanced oxidation (IEO). Due to the oxide entirely covering the trench shoulder by a self-aligned process, the proposed structure has notable merits: (i) the anomalous hump current in $I_{\text{d}}$-$V_{\text{g}}$ subthreshold characteristics is suppressed even in a narrow-channel transistor and (ii) the proposed structure provides less susceptibility to crystal defect generation. These can facilitate fabrication of controllable devices. In addition, a deeply implanted channel stopper yields a low parasitic capacitance for fast device operation and excellent isolation performance characteristics such as low field penetration and low punch-through current. These are attributed to the effect of the electric field shield.
- 2003-04-15
著者
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Kidera Toshirou
Research Center For Nanodevices And Systems Hiroshima University
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Takase Akihiro
Research Center For Nanodevices And Systems Hiroshima University
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Sunami Hideo
Research Center For Nanodevice And Systems Hiroshima University
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Sunami Hideo
Research Center for Nanodevices and Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashi-Hiroshima, Hiroshima 739-8527, Japan *Present address: Semiconductor Company, Toshiba Corp., Shinsugita 8, Isogo, Yokohama, Kanagawa, Japan
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Takase Akihiro
Research Center for Nanodevices and Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashi-Hiroshima, Hiroshima 739-8527, Japan *Present address: Semiconductor Company, Toshiba Corp., Shinsugita 8, Isogo, Yokohama, Kanagawa, Japan
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Kidera Toshirou
Research Center for Nanodevices and Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashi-Hiroshima, Hiroshima 739-8527, Japan *Present address: Semiconductor Company, Toshiba Corp., Shinsugita 8, Isogo, Yokohama, Kanagawa, Japan
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