Characterization of Polycrystalline Silicon Thin Film Transistors Fabricated by Ultrahigh-Vacuum Chemical Vapor Deposition and Chemical Mechanical Polishing

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概要

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• A high performance top-gate thin film transistor (TFT) has been fabricated using an as-deposited polycrystalline silicon (poly-Si) film by ultrahigh-vacuum chemical vapor deposition (UHV/CVD) followed by chemical mechanical polishing (CMP). In this process, due to the ultraclean environment and very low-pressure deposition of UHV/CVD, high-quality poly-Si films can be obtained and no long-term or post-recrystallization in channel films is needed. Maximum field effect mobilities of 58 cm2/V·s and 98 cm2/V·s for p- and n-channel TFTs, respectively, an ON/OFF current ratio of 1.1×107 for both p- and n-channels, and threshold voltages of -0.54 V for p-channel and 0.36 V for n-channel devices, respectively, are achieved. Finally, an analytical model of poly-Si TFTs was used to simulate the gate-voltage-dependent activation energy on the threshold and above the threshold regions and showed good agreement.

• Publication Office, Japanese Journal of Applied Physics, Faculty of Science, University of Tokyoの論文
• 1997-07-15

著者

• Chang Chun-yen

  Department Of Electronics Engineering & Institute Of Electronics National Chiao Tung Uiversity

• Lei Tan

  Department Of Electronic Engineering National Chiao Tung University

• Chen Liang-po

  National Nano Device Laboratories

• Lin Hsiao-yi

  Department Of Electronics Engineering & Institute Of Electronics National Chiao Tung University

• Tseng Hua-chou

  Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung University

• Cheng Juing-yi

  Department Of Electronics Engineering & Institute Of Electronics National Chiao Tung University

• Chang Chun-Yen

  Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University,

• Lei Tan

  Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University,

• Chen Liang-Po

  National Nano Device Laboratories, Hsinchu 300, Taiwan, Republic of China

• Lin Hsiao-Yi

  Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University,

• Tseng Hua-Chou

  Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University,

• Cheng Juing-Yi

  Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University,

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